Motivation

The author of this library has been working in ASIC design verification for the past decade. ASIC Hardware designs are typically written using languages like Verilog or VHDL, called Hardware Description Languages(HDL). These languages describe registers and wires and combinational logic, for simulation in a simulator. These languages are intended for manipulating logic, whose smallest divisible component is the bit.

The verification of those chips typically involves some sort of comparison against a software architectural model, which describes the functional behavior of the design. These models are nearly always written in some form of C / C++.

Unfortunately describing low level bit operations within C++ does not have the same elegance as within an HDL. Bools are used in place of bits, and unsigned integral are used to store bit lengths, that don't necessarily share the same size as the type they model. Manipulating bits within these types involves shifting, masking, and casting operations, whose description often times loses its semantic meaning.

The motivation ( finally ) behind designing this library was to be able to have an open source library which would allow for the clear semantic meaning to manipulating bits within a arbitrary length type. This library is intended to make modeling an 292 bit type or a 3 bit type as easy a using the built in types of C++.